huge hardware demands of artificial intelligence (AI) applications are pushing the physical and structural limits of semiconductors. But researchers have created a three-dimensional silicon chip that they propose as a solution.
In a new study published May 27 in the journal NatureScientists have discovered a way to pack more computing power into a chip by stacking silicon circuits in multiple layers in a way that doesn’t impact performance.
Stacking chips vertically, known as 3D integration, is more efficient than traditional 2D chips, where silicon circuits are spread out over a single surface. This is because stacking reduces the distance that data must travel and reduces the power required for data transmission.
The researchers’ 3D chip uses ultrathin silicon membranes and low-temperature manufacturing techniques to overcome the challenges of current chip architectures.
“Our method is not only easy to implement at low cost, but it has several advantages over previous methods of stacking silicon wafers,” king kaoThe study’s first author and materials science and engineering professor at the University of Illinois Urbana-Champaign said in a statement.
extension of moore’s law
Since the 1960s, ensuring that electronics can handle more demanding applications has meant making transistors smaller so that more can be packed onto the same chip. But, as Kao pointed out, the number of transistors doubles every two years – a principle known as Moore’s law – is becoming less viable.
“If you look at the actual size of transistors, they are not getting smaller, especially in terms of their contact gate pitch,” Cao said in the statement — defined as the combined width of one transistor gate and the space required to separate it from the next.
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“This is because we are increasingly limited by the intrinsic physical properties and fundamental laws of silicon quantum mechanics. If we want to continue the trend of increasing the processing power of our microprocessors, we need to start thinking beyond simply squeezing more devices onto a single surface.”
The researchers believe that vertical integration across multiple layers is the best way to guarantee that engineers can continue to obey Moore’s Law, because this approach makes room for more transistors on a chip.
“Today storing one bit of information requires six microelectronic devices called transistors in a single plane,” Cao explained, suggesting that the only way to solve congestion, like in a densely populated city, is to build upwards. “You get the same functionality, but the spatial footprint is reduced while making communication between layers faster and more efficient.”
Scientist Gordon Moore seen with a graph representing Moore’s Law.
relief from heat problem
Of course, stacking is nothing new, but vertical integration – building layers directly on top of each other – can create thermally denser packages. In the study, the researchers said that manufacturing high-quality silicon chips requires temperatures as high as 1,832 degrees Fahrenheit (1,000 degrees Celsius).
However, once the first chip layer is complete, the metal wiring used to connect further layers can be destroyed by such high temperatures. As a result, the “thermal budget” — the maximum amount of heat that can be tolerated before degradation begins — is 752 F (400 C) for any additional layer, Cao said. This may result in performance and reliability issues.
According to the researchers, manufacturers have tried to avoid this problem when creating 3D stacked silicon chips by using alternatives to single-crystalline silicon for the upper layers. These materials include amorphous and nanocrystalline metal oxides, carbon nanotubes and polycrystalline silicon, but they can lead to performance and reliability issues, the scientists said in the study.
To overcome this challenge, Cao and his team adopted an approach called “monolithic integration” – a process in which all chip components are fabricated on a single piece of substrate, as opposed to manufacturing them separately and then joining them together later.
To make each chip, the researchers created ultrathin silicon nanomembranes, which they transferred onto a bottom-layer substrate using a roll laminator.
The maximum temperature required to produce a strong bond using this method was only 392 F (200 C) – five times less than the heat normally required. The membranes they transferred were also only 10 nanometers thick or less—about the size of a protein—compared to the roughly 500-to-700-micrometer (500,000 to 700,000 nanometers) thickness of a typical wafer. Because they are thin, these membranes are mechanically flexible to conform to the underlying surface, Cao said.
The result of this process was a 3D chip with three layers, each containing 625 transistors. It pales in comparison billions of transistors It can be stuffed into chips already on the market, but the researchers believe their technology boasts power efficiency benefits. The electrical current flowing through the chip has proven to be at least three to four times higher than that of monolithic chips made from alternative materials.
The big question is whether their 3D silicon chip can make the leap from the laboratory to commercial applications. While the research demonstrates the potential of a chip with three stacked layers, scientists suggested that many more layers could be added in future iterations.
Bao Lam, Yung Man Yu, Hunjun Nam, Hsu-Chih Ni, Shomik Chatterjee, Shalu Rakheja, Jian-Min Zuo, Qing Cao. Monolithic three-dimensional integration of silicon transistors. Nature2026; DOI: 10.1038/s41586-026-10496-6
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